MEMS Electrostatic Energy Harvester Developed by Simultaneous Process for Anodic Bonding and Electret Charging

In this paper, we present a new structure and a process for electrostatic energy harvesters fabricated using a silicon-on-glass wafer. Conventional electret-based MEMS energy harvesters are produced using a silicon-on-insulator (SOI) wafer, which is inevitably accompanied by parasitic capacitances across the buried oxide layer. The new harvester, on the other hand, can be formed by individually developing silicon and glass parts and subsequently putting them together by anodic bonding, thereby virtually eliminating parasitic capacitance. Special caution is taken not to cause the destruction of the electret layer during high-temperature anodic bonding. The device has been successfully fabricated and experimentally confirmed to function as an energy harvester. This silicon-on-glass structure is beneficial in not only suppressing the parasitic capacitance but also increasing its output power compared with those made by the conventional SOI-based process.


Introduction
The operating power for wireless sensor nodes is usually provided through batteries for ease of installation. (1)However, batteries require periodical replacement when depleted, leading to extra maintenance and labor cost. (2)As their alternative, power sources called energy harvesters that generate energy from the surrounding environment have attracted attention as an enabling technology to realize, for example, a sensor network for infrastructure monitoring. (3)There are various types of ambient energy source, among which environmental vibration is popular.The power density of vibrations is not as high as that of sunshine, but it ubiquitously exists regardless of the weather conditions (4) and the time of day.19)(20)(21)(22)(23)(24)(25)(26)(27)(28)(29)(30)(31)(32) Amongst them, electrostatic energy harvesters using the permanent electrical charge or socalled electret can effectively convert small mechanical vibrations into electrical power, owing to the advantage that the mechanical resonator part and power-generating electrodes can be independently designed to optimize the harvester performance as a velocity-damped resonance generator (VDRG). (33)igure 1(a) shows a photograph of an electret-type vibrational energy harvester reported elsewhere. (34)The device structures were produced by the deep reactive ion etching (DRIE) of a silicon-on-insulator (SOI) wafer.The scanning electron microscopy (SEM) image of the electrodes and electrical interconnections is shown in Fig. 1(b).Symmetric comb structures (total of 900 pairs on each side) were fabricated using the top silicon layer.Figure 1(c) schematically shows the comb electrodes coated with a silicon oxide layer of electret doped with potassium ions.The device generates electrostatic inductive currents when the relative distance between the comb electrodes changes owing to mechanical vibrations.As reported elsewhere, (34) the output power is enhanced using a higher electret potential (−200 V with respect to the electrically grounded movable electrodes) and a large surface area of the electrodes (i.e., using a high aspect ratio of the comb fingers of ~40).Owing to recent improvements, the maximum deliverable power of 435 µW has been realized from the input vibrations of 138 Hz at 0.2 G. (35) Although the use of an SOI wafer is beneficial for forming mechanically movable electrodes, the electrical interconnection patterns formed in the SOI layer inevitably have parasitic capacitances with respect to the handle layer as illustrated in Fig. 1(d).Figure 1(e) shows the output power when the buried oxide (BOX) layer of different thickness is used.The output increases when the BOX layer is made thicker and the parasitic capacitance decreases.The stray capacitance can be lowered to some extent using an SOI of a thick BOX layer as reported elsewhere. (36)Nonetheless, an equivalent circuit model suggested that the BOX layer thickness needed to eliminate the effect of the stray capacitance would be more than 10 µm, which is not practically available from a cost and residual-stress viewpoint of SOI wafers.
In this paper, we describe an electrostatic energy harvester formed in a silicon-on-glass (SoG) structure to virtually eliminate the effect of parasitic capacitance.Presuming that the SoG device in this work is equivalent to the SOI device with a very thick BOX layer, the output is estimated to have been improved more than ×1.5 compared with the SOI device with a 2-µmthick BOX layer.A fabrication process of anodic wafer bonding that is compatible with the electret forming is discussed in detail.To the best of the authors' knowledge, this is the first report of a MEMS vibrational energy harvester made as an SoG layer structure.

SoG-type Electrostatic Energy Harvester
Figure 2(a) shows a schematic of an electrostatic energy harvester produced using a silicon substrate bonded on a Tempax ® glass substrate, instead of an SOI wafer.The electret-comb electrodes and suspensions functioning as a VDRG are located in the silicon substrate.On the other hand, the glass substrate functions as an electrically insulating frame with a cavity to avoid friction with the movable electrode formed in the SOI substrate.These two substrates are firmly joined by anodic bonding.
Figure 2(b) shows the cross-sectional diagram, corresponding to structures in the red box shown in Fig. 2(a).When using an SOI wafer, the active and handle layers face each other having an electrical insulator in between, which produces a series of parasitic capacitors connected through the handle wafer.When using an SoG substrate, on the other hand, the comb electrodes formed in the silicon substrate are mechanically fixed by the insulating glass frame without having another silicon handle layer, thereby virtually eliminating the internal parasitic capacitance.As a result, the inductive charge is delivered to the load resistance without bypassing the reactive current.
In this work, the silicon oxide film doped with potassium ions is utilized as an electret film because it can be formed even on the sidewalls of comb electrodes.Anodic bonding and electret charging are schematically shown in Figs.2(c-1) and 2(c-2), respectively.When bonding a sodium-doped Tempax ® glass and a silicon wafer, sodium ions move away from the bonding interface (i.e., the anode) owing to the high electrical field and temperature as high as 500 ℃.(39) These two processes are substantially the same from an ion-migration viewpoint.We only need to figure out a total process so as not to mitigate the built-in potential of anodic bonding during the subsequent electret formation.

Fabrication
Before discussing the details, we show a brief outline of the whole process using the schematics shown in Fig. 3.The top views of the silicon and glass substrates are shown in the upper part of the figure, whereas Figs.3(A)-3(F) show the process flows of two cross sections a-a' and b-b'.Photographs on the right-hand side are the chip appearances during the process.
In step (A), the process begins with a silicon wafer of 525 μm thickness.A silicon nitride (SiN) layer of 200 nm thickness is deposited on both the top and bottom surfaces of the wafer by low-pressure chemical vapor deposition (LPCVD).In step (B), the SiN layers are patterned using reactive ion etching (RIE) equipment (Samco Inc., RIE-10NR); the SiN layers serve as a protective mask against the local oxidation of silicon (LOCOS) process later.The half-etching of silicon is performed from the back side of the wafer by deep reactive ion etching (DRIE) (SPP Technologies Co., Ltd., Predeus), leaving only 50 µm of silicon.The purpose of this half-etching is to minimize the surface damage that will occur at the final etching process separating the movable and fixed electrodes.After half-etching, the full etching of the comb patterns is carried out from the top side of the wafer.In this etching process, a soft dummy mask is added to temporarily protect the wider aperture, aside from a hard mask, to cope with the loading effect resulting from the different aperture widths in the comb electrode patterns.(39) In step (D), the SiN patterns on both sides of the silicon substrate are removed by RIE, partially exposing the silicon surface for later use.In step (E), a 500-µm-thick Tempax glass is prepared by sand blast to form a 160-µm-deep recess.The silicon substrate is then mounted on the glass substrate and put together by anodic bonding.In this process, the two substrates are annealed directly on a heater and electrically biased with 700 V dc for 15 min.
In step (F), another half-etching is performed by DRIE from the top side of the SoG structure; the SiN film formed for the LOCOS process is removed by RIE, and the silicon areas that have been hidden under the SiN film reappear, allowing the subsequent DRIE using the oxide patterns as an etching mask.The trenches formed in the silicon substrate isolate the movable electrodes from the fixed ones.

Sacrificial photoresist masks for uniform trench DRIE
In this section, we describe the fabrication method for the tall comb structures using a silicon wafer.Vibrational energy harvesters are known to deliver relatively large power when excited at large strokes, and therefore utilizing electrodes of long comb fingers is preferred.Such an electrode design, however, inevitably requires etching mask patterns of different aperture widths, including the small gap between the comb fingers and a relatively wide opening between the fingertip and the comb pocket.
The mixed use of different aperture sizes usually causes different trench etching rates and profiles including lateral notches, leading to inhomogeneous trench depths and profiles distributed over the wafer, usually referred to as aspect-ratio-dependent etching (ARDE). (40)To mitigate this effect, we utilized photoresist masks (S1805, Microposit) as a soft compensation mask filling the gap made in the regular aluminum mask patterns for the comb electrodes, as shown in Fig. 4(a).
Figure 4(b) shows the cross-sectional views of trench etching using the combination of the photoresist and aluminum masks.The soft photoresist mask temporarily protects the wide aperture between the comb electrodes until the latter half of etching; the area protected under the photoresist is eventually removed as a final shape by time-delayed etching.The opening between the photoresist and an aluminum mask is intentionally designed to be equal (15 µm) to that between the aluminum masks shown in Fig. 4(c), and therefore, the etching is programmed to finish at the same time throughout the wafer without causing lateral notches at the bottom of the trenches.The top and rear surfaces of electrodes are shown in Figs.4(d-1) and 4(d-2), respectively; no notch etching is seen, and the mask patterns have been transferred to the bottom with high fidelity.In the device, the comb electrode thickness is 525 µm, which is identical to the wafer thickness.

Trench for electric insulation
Most electrostatic energy harvesters made of an SOI wafer use electrically isolated movable and fixed electrodes that are placed on a handle wafer with an electrical insulator layer in between, so that they can be individually biased at arbitrary voltages.The electrodes in an SoG wafer, on the other hand, are made out of a single silicon wafer; for this reason, any patterns surrounded by a trench would have fallen off the substrate.In this work, therefore, we developed a process to create isolation trenches after bonding the single silicon wafer onto a glass substrate.
The total process was deliberately designed not to cause excess production errors in the outline dimensions of the electrodes.First, we utilized half-etching from the rear side of the single silicon wafer by DRIE before wafer bonding, leaving an unetched thickness of 50 µm on the front side as shown in Fig. 3(B).The silicon nitride layers on both surfaces of the wafer are used to protect a few spots of the silicon area from the subsequent LOCOS process so that they can be used as bonding pads later.After oxidation, the silicon nitride mask was removed by RIE using CF 4 gas.The RF power and the pressure were set to be 100 W and 5 Pa, respectively.During this process, the etching into the silicon oxide layer was negligible owing to the high etching speed contrast between silicon and silicon oxide.The silicon nitride layer also protects another part of the silicon surface so that the remaining 50-µm-thick silicon layer can be etched from the front side to complete the electrical isolation between the electrodes.This additional DRIE takes place after bonding the silicon wafer onto the glass substrate, and therefore, the individual electrodes are firmly fixed without causing mechanical defects.
Figure 5(a) shows a photograph of the entire chip after forming the trenches from the front side.The surface is the silicon oxide layer including potassium ions.Figure 5(b) indicates the area where there are trenches and the electrode pad.The trenches with an opening of 258 µm width are formed into the substrate down to the interface to the glass substrate.Figure 5(c) shows the three-dimensional profile of the electrode pad measured using an optical microscope (Keyence, VHX-7000).The pad was recessed by 40 µm from the top face of the silicon by the final silicon etching, but it did not affect the wire-bonding result.Figure 6 shows the photographs before and after separating the electrodes.The top silicon oxide layer is slightly thinned by the  final etching, and the interference color has changed from violet to green.Owing to the halfetching performed in advance, the total etching time has been shortened to minimize the thinned film of the silicon oxide layer, which still functions as an electret.Isolation trench etching was successful without causing the deformation of outline dimensions of the comb structures.

Simultaneous process for anodic bonding and electret charging
Since the electret forming process also utilizes high-temperature annealing, silicon and Tempax ® glass substrates that have been anodically bonded might fall apart owing to the rediffusion of the sodium ions.Considering that the physical mechanism of anodic bonding is substantially the same as that of electret formation, which only uses different species of ions, we have developed a method of charging the electret without causing the delamination of the anodically bonded interface, i.e., applying voltage to maintain the bonding between the wafers while electrically biasing the electrodes for electret charging.
The electrical setup using three tungsten probes applying voltage to the chip is shown in Fig. 7(a).Two voltages, 700 and 800 V, are applied to the chip frame and fixed electrodes, respectively, as schematically shown in Fig. 7(b), thereby electrostatically holding the entire chip on the glass substrate.At the same time, the said voltages are applied to the fixed and movable electrodes as shown in Fig. 7(c), leaving the differential voltage of 100 V across the air gap to form an electret skin on the fixed electrodes.
To verify the polarization process, the surface potential formed by the electret was examined using a surface potential profiler (TREK Japan, Model 344) as shown in Fig. 8(a).The sensor head was held and scanned over the chip as shown in Fig. 8(b) to monitor the space-averaged potential within the area of the sensor head.Figure 8(c) shows the result of potential measurement.The potential in the middle part of the chip was as small as −12 V, reflecting the fact that the suspended electrodes are pulled down to GND; the surface potential profiler used in this work has a sensing head of as large as 1 cm, and the potential distribution within this area is averaged for sensing.The potentials measured near the corners of the chip were relatively high, −80-−133 V, because the silicon parts fixed on the glass substrate retain higher potentials for anodic bonding as well as electret formation.
Figure 9(a) shows a photograph of the completed device.The size of the silicon part is 12.5 × 14.3 mm 2 , and that of the glass part is 18.5 mm 2 .After polarization, the chip was glued onto the printed circuit board and then the electrode pads were interconnected by wedge wire bonding.
Figures 9(b) and 9(c) show photographs of the rear side of the chip.The grainy silver surfaces seen in the figure show the anodically bonded interface.Trenches for electrical isolation can be seen between the silicon structures.In addition, the anchor part of the movable electrode was found to have been firmly fixed on the glass part.The springs and comb electrodes were off the focal plane owing to the cavity formed on the glass surface, which can be seen through the glass substrate from the rear side.

Experimental Results
To verify the power generation performance, the completed chip was tested using the electromagnetic shaker (Emic, 9514-AN/SD 373-A, DCS-98S Smart) as shown in Fig. 10(a).A high-speed microscope camera (Keyence VW9000SP) was used in the upright position above the shaker to monitor the harvester's mechanical motion.Figure 10(b) shows the snapshot images of the chip in operation when an input vibration was applied in the lateral direction with a magnitude of 0.8 G at 1694 Hz.The movable electrodes were found to oscillate to the full scale, while the fixed electrode seemed to be stationary, implying that the incoming oscillation   was effectively amplified within the suspended resonance system to cause a large oscillation of the suspended mass.Figure 10(c) shows the detailed snapshot images of the comb electrodes under an acceleration of 1.5 G.The electrodes' motion was close to the maximum displacement of ±150 µm.
Figure 11(a) illustrates the electrical circuit for the measurement of the output power.A current-voltage converter (Hamamatsu, C7319) was used to electrically decouple the device under test from the input impedance of the oscilloscope.An experimentally observed shortcircuit current waveform is shown in Fig. 11(b) when the chip was shaken by an acceleration of 0.8 G at 1694 Hz.This waveform suggests that the movable electrodes oscillated with a sinusoidal wave similar to the input acceleration waveform.Figure 11(c) shows the experimental result of the output power as a function of the input acceleration, when the chip was loaded by 3 MΩ and excited to the stroke limit at 1694 Hz.From this result, the output power was found to have been increased by the square of the input acceleration.In addition to this, no mechanical failure was observed on the device even when the input acceleration was increased to 1.5 G, where the mechanical stroke reached its limits.

Conclusions
In this work, an electrostatic energy harvester formed in an SoG structure was proposed as a new design to mitigate the effect of internal parasitic capacitance.The newly developed structure was realized by the combination of (1) sacrificial photoresist masks for uniform trench DRIE, (2) deep trenches for electrical isolation in a single silicon wafer, and (3) the simultaneous process of anodic bonding and electret charging.After polarization, we confirmed that the device surface had a potential of approximately −100 V, which was close to the differential voltage between the voltages applied for electret charging and anodic bonding.Electrostatic induction current was observed as expected during mechanical excitation.No mechanical delamination of layers was observed even when the mechanical stroke reached its limits under hard excitation of 0.8 G at 1694 Hz, indicating a sufficiently large bonding strength for vibrational energy harvester applications.When the chip was loaded by 3 MΩ and operated at the resonance, the output power was enhanced to 3 nW at 1.5 G.In conclusion, electrostatic energy harvester structures fabricated using the conventional SOI wafer can be replaced with the newly developed SoG structures to suppress the reactive power that does not contribute to the net output power.

Fig. 1 .
Fig. 1. (Color online) Energy harvester composed of comb electrodes covered with electrets, which is developed by DRIE of an SOI wafer.(a) Photograph of the entire chip.(b) SEM image of the comb electrodes and electrical interconnection lines.(c) Schematic of the comb electrodes covered with a silicon oxide electret film doped with potassium ions.(d) Comb electrodes and equivalent electrical circuit.The two electrical contact pads on the left-and right-hand sides are coupled via the handle layer of silicon forming a series of stray capacitances.(e) Output power when the BOX layer behaves as an internal parasitic capacitance.

Fig. 4 .
Fig. 4. (Color online) (a) Two types of dry etching mask for the comb structure formed in a silicon wafer.Aluminum and photoresist (S1805, Microposit) are used as a hard mask and a soft dummy mask, respectively.Cross sections of the etching process flow in the (b) narrow-and (c) wide-aperture areas.(d-1) Top and (d-2) rear surfaces of the comb fingers after etching.

Fig. 5 .
Fig. 5. (Color online) (a) Entire chip after forming the trenches for electrical isolation.(b) Trenches and the electrode pad.(c) Three-dimensional shape data of the electrode pad measured using a microscope (Keyence, VHX-7000).

Fig. 7 .
Fig. 7. (Color online) Simultaneous process for anodic bonding and electret charging.(a) Experiment setup in the vacuum chamber.(b) Top and (c) side views of voltage application.

Fig. 8 .
Fig. 8. (Color online) (a) Entire system for determining the surface potential.(b) Close-up view of the measurement probe.(c) Potential distribution measured using the surface potential profiler (TREK Japan, Model 344).

Fig. 9 .
Fig. 9. (Color online) (a) Photograph of the energy harvester chip.(b) Rear side view of the bonded part.(c) Rear view of the bonded and suspended parts.

Fig. 10 .
Fig. 10.(Color online) (a) Photograph of the energy harvester chip under vibration test.Snapshot images of the (b) elastic springs and (c) comb electrodes in operation taken with a high-speed camera.

Fig. 11 .
Fig. 11.(Color online) (a) Circuit diagram for measuring the output current and power.A load resistance is inserted between the output terminal of the chip and the virtual ground point of the amplifier.(b) Short-circuit current waveform under a sinusoidal oscillation with acceleration of 0.8 G at 1694 Hz.(c) Output power as a function of the input acceleration when the energy harvester was loaded by 3 MΩ and operated to the stroke limit (±150 µm) at 1694 Hz.