Interconnection Characteristics of Rivet Packaging for Radio Frequency Microelectromechanical Systems Applications

In this paper, we present an alternative method of rivet packaging for radio frequency microelectromechanical system (RF MEMS) devices and evaluate its electrical characteristics. The rivet packaging enables not only encapsulation but also through-via interconnection at the same time. Moreover, it is possible to achieve a wafer-level process. The electrical performance was evaluated using Cu hollow-filled through-via interconnection. The overall insertion loss of the through-via interconnection from the bottom CPW to the top CPW decreased from 0.04 to 0.11 dB at 2 GHz and from 0.06 to 0.23 dB at 5 GHz.


Introduction
System-in-Package (SiP) is defined as the vertical stacking of similar or dissimilar ICs with or without embedded active and passive components. Devices must be threedimensionally (3-D) assembled and interconnected to obtain the smallest volume. (1) To achieve SiP technology, 3-D interconnection technologies, such as 3-D wiring, wireless interconnection, blind vias, and silicon through-vias, required. (2) In particular, the silicon through-via interconnection method is associated with SiP technology, such as the flip chip and the stacking technology. (3) In silicon through-via interconnection, device pads are electrically passed out of the encapsulation along the shortcut of the through-via.
In the silicon through-via interconnection approach, there are some problems to be addressed. (4)(5)(6)(7) The well-known "Bosch process" enables the realization of a high-aspectratio silicon through-via structure using the cycles of the combination of isotropic etch, surface protection deposition, and anisotropic etch of the passivation layer. However, a notch is basically generated from the charge build-up on the dielectric surface at the bottom. This notch structure will disturb the electrical interconnection.
Moreover, the silicon through-via structure is filled with a conductive material for the electrical interconnection. The metal-filled silicon through-via structure is mechanically vulnerable to thermal expansion because of the difference in the coefficient of thermal expansion (CTE) between silicon and metal. If it has a seam or an air-void inside, it will show the worst mechanical stability. The failure occurs in the metal-filled silicon through-via.
In particular, the silicon through-via interconnection for RF MEMS package has to not only solve these problems but also have good RF characteristics. It is very important to pass the signal outside with minimal loss using the RF MEMS package. The electrical performance of the packaged device is evaluated on the basis of its characteristic value according to the application. Basically, the average resistance or RF-loss per unit length of the feed through passing from the terminal pads to the final pad can be the representative value.
In this paper, we present not only the rivet packaging method that was previously presented (8,9) but also its electrical characteristics, to solve the problem of silicon throughvia, improve RF-loss characteristics, and prove its usefulness.

Rivet packaging
Rivet packaging uses two types of wafer; one is a male wafer having a relatively thick solder as a donor, the other is a female wafer as an acceptor having structures similar to a mushroom or a through-via structure. The solder as the donor, when it melts, reflows along the wetting layers on under bump metallization (UBM). When it meets on the walls of the female wafer as the acceptor, the sidewall bonding begins and stops at the corner of the wall owing to the absence of a wetting layer as described in Fig. 1. Finally, the end of the solder become spherical owing to the tendency to minimize the surface energy, and consequently, generates a rivet structure. Therefore, in rivet packaging, both the encapsulation of the mushroom structure and the electrical interconnection of the through-via are simultaneously achieved.

Design
The proof-of-concept structure is shown in Fig. 2. The electrical performance of the rivet packaging method is studied using the coplanar waveguide (CPW)-to-CPW transition with a Cu hollow-filled through-via. The signal lines and ground lines on both wafers are designed to provide the characteristic impedance of 50 Ω. The two wafers are high-resistivity silicon (HRS, 300 μm thick, > 20,000 Ω•cm), which were chosen owing to their ease of processing, excellent mechanical properties, and good electrical performance. (10) The CPW line was an electrically interconnected through-via obtained by the rivet packaging method. The RF signal of the CPW line goes from the input port to the output port through the Cu hollow-filled through-via, as shown in Fig. 3.
The layout of the male wafer is shown in Fig. 4. The layout of the female wafer and its cross-sectional design are shown in Figs  of about 70 µm height is electroplated for the reflow process. The antiwet layer was designed to be of 15 µm width restricts the solder reflow. The radius of the Sn solder region was designed to be 5 µm shorter than that of the through-via, and the inner radius of the anti-wet layer was 5 µm longer. The length of the signal line between the input and output ports was 1 mm, and the ground plane was 4 mm 2 in total.

Simulation
The physical structure was simulated using the full 3-D software of Ansoft's High-Frequency Structure Simulator (HFSS). The 3-D model of HFSS is shown in Fig. 7, and the ports were matched to a characteristic impedance of 50 Ω. The CPW configurations were designed for operation from 1 to 10 GHz.
The simulation results are shown in Fig. 11. The results of CPW and the rivetpackaged CPW showed that the presence of the through-via caused mismatches between CPW transitions and then decreased insertion loss, owing to the presence of parasitic inductance and capacitance.

Fabrication of Wafers
The fabrication of the male and female wafers is based on a previously reported paper. (9) The process flow of rivet packaging is shown in Fig. 8. The mushroom structure in the seal line and the through-via structure are fabricated on the female wafer, and a pure Sn solder of about 70 μm height is electroplated on the male wafer. The through-via and pure Sn solder are successfully fabricated, as shown in Fig. 9. Two wafers are assembled into a rivet formation with appropriate force applied and then heated to 250°C in N 2 atmosphere. They are bonded following the principle of solderreflow phenomena for making rivet structures. SEM images of the rivet package are shown in Fig. 10. The solder has a dome shape, which indicates that riveting using a solder is successfully achieved. The top electrode is fabricated by Cu electroplating using DFR photolithography on the bonded wafer. The through-via is also electroplated simultaneously at 20 μm thickness.

Measurement results
The measurement results are shown in Fig. 11. The fabricated CPW lines had an insertion loss of 0.1 dB up to 10 GHz. However, the overall insertion loss of the through-via interconnection decreased from 0.04 to 0.11 dB at 2 GHz and from 0.06 to 0.23 dB at 5 GHz. The higher the frequency, the larger the decrease in insertion loss. It is considered that the decrease resulted from the impedance mismatch caused by the parasitic inductance and capacitance of the through-via.

Discussion
Considering its insertion loss per unit millimeter, the results are valuable for application in RF-MEMS. However, at high frequencies, a better matching network for the design of through-vias must be investigated. The through-via design has to be compensated for by introducing appropriate capacitance at the transition point.
The measured S-parameter S21 agreed well with the simulated results from HFSS. Consequently, this result showed that HRS has merits as a suitable substrate for devices operating within microwave frequencies. Moreover, it is noted that the Sn solder material and the through-via size do not considerably affect the RF characteristics because the very thick Cu metal with high conductivity does not markedly affect the decrease in the insertion loss.

Conclusions
We successfully demonstrated an alternative packaging method, namely, the "rivet packaging method" for MEMS packages. It enables not only encapsulation but also through-via interconnection simultaneously. The electrical performance was evaluated using a Cu hollow-filled through-via interconnection. It was simulated by HFSS and measured using a network analyzer. The measured S-parameter S21 agreed well with the simulation results from HFSS. The overall insertion loss of the through-via interconnection from the bottom to the top CPW decreased. Considering its insertion loss per unit millimeter, the results are valuable for application in RF-MEMS. However, at high frequency, a better matching network for through-vias must be designed, which can be compensated for by introducing appropriate capacitance at the transition point.