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Vol. 32, No. 8(2), S&M2292

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Sensors and Materials, Volume 32, Number 10(3) (2020)
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pp. 3373-3382
S&M2345 Research Paper of Special Issue
https://doi.org/10.18494/SAM.2020.2776
Published: October 30, 2020

Influence of Environmental Conditions on Electrical Stability of Pentacene Thin-film Transistors with Cross-linked Poly(4-vinylphenol-co-methyl methacrylate) Gate Dielectric Layer [PDF]

Jyothi Chintalapalli, Joel Ndikumana, Sungkeun Baang, and Jaehoon Park

(Received March 2, 2020; Accepted April 16, 2020)

Keywords: thin-film transistor, pentacene, poly(4-vinylphenol-co-methyl methacrylate), bias stress, environmental condition

Gate-bias stress causes changes in the electrical stability of thin-film transistors (TFTs), and this can degrade the device performance. This research highlights the effects of environmental conditions on the electrical stability of pentacene TFTs in which cross-linked poly(4-vinylphenol-co-methyl methacrylate) (PVP-co-PMMA) was utilized as a gate dielectric layer. Under negative gate-bias stress, the fabricated TFTs exposed to ambient air showed a positive threshold voltage shift, whereas the devices under vacuum exhibited a negative threshold voltage shift. Furthermore, consecutive on/off switching operation of pentacene TFTs under ambient air induced an increase in the on-state drain current. These results are explained through the interaction between water molecules and PVP-co-PMMA, which causes the accumulation of holes in the TFT channel region having higher conductance.

Corresponding author: Sungkeun Baang, Jaehoon Park

This work is licensed under a Creative Commons Attribution 4.0 International License.

Cite this article
Jyothi Chintalapalli, Joel Ndikumana, Sungkeun Baang, and Jaehoon Park, Influence of Environmental Conditions on Electrical Stability of Pentacene Thin-film Transistors with Cross-linked Poly(4-vinylphenol-co-methyl methacrylate) Gate Dielectric Layer, Sens. Mater., Vol. 32, No. 10, 2020, p. 3373-3382.