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S&M4087 Research Paper of Special Issue https://doi.org/10.18494/SAM5534 Published: July 4, 2025 Analyzing Noise Margin Degradation in Subthreshold Nanosheet Transistor Logic Gates: An Interface Quasi-Fermi Potential Model for Interface-trapped Charge Effects [PDF] Juin J. Liou, Yimu Yang, and Te-Kuang Chiang (Received January 15, 2025; Accepted March 31, 2025) Keywords: interface quasi-Fermi potential (IQFP), noise margin, subthreshold logic gate, interface-trapped charges, nanosheet transistor
On the basis of the continuity of subthreshold current at the interface of trapped charges in the channel between fresh and damaged regions, a new interface quasi-Fermi potential (IQFP) model for the nanosheet FET with interface-trapped charges (ITCs) is developed. With the IQFP, the subthreshold current degraded by the ITCs for both N-FET and P-FET can be completely developed. We found that the IQFP can be strongly affected by both the distribution and polarity of the ITCs. Owing to the distribution of positive/negative ITCs near the drain side for N-FET/P-FET, the decreased threshold voltage will cause noise margin (NM) degradation. In contrast, the threshold voltage will be increased by the distribution of negative/positive ITCs near the source side for N-FET/P-FET, which resists the degradation of the NM. The NM caused by the balanced transistor strength between P-FET and N-FET can be monitored using the IQFP. This model can also be extended to other multi-channel-potential FETs comprising the subthreshold logic gate.
Corresponding author: Te-Kuang Chiang![]() ![]() This work is licensed under a Creative Commons Attribution 4.0 International License. Cite this article Juin J. Liou, Yimu Yang, and Te-Kuang Chiang, Analyzing Noise Margin Degradation in Subthreshold Nanosheet Transistor Logic Gates: An Interface Quasi-Fermi Potential Model for Interface-trapped Charge Effects, Sens. Mater., Vol. 37, No. 7, 2025, p. 2793-2802. |