pp. 2323-2331
S&M1935 Research Paper https://doi.org/10.18494/SAM.2019.2360 Published: July 19, 2019 Optimization of Ferroelectric Phase in Poly(vinylidene fluoride co-hexafluoropropylene) under Different Annealing Conditions [PDF] Chintalapalli Jyothi, Jaehoon Park, and Eui-Jik Kim (Received March 6, 2019; Accepted June 13, 2019) Keywords: field-effect transistors, poly(vinylidene fluoride co-hexafluoropropylene), annealing temperature, hysteresis loop
Field-effect transistors (FETs) are considered promising devices for future development owing to their application in large-area electronics. In this research, we focus on the fabrication and optimization of the ferroelectric phase of an FET by utilizing poly(vinylidene fluoride co-hexafluoropropylene) [P(VDF-co-HFP)] as a gate insulator and pentacene as an organic semiconductor under different annealing conditions. The FET was fabricated by mixing P(VDF-co-HFP) with a preformulated concentration of methyl ethyl ketone and by spin coating this mixture onto the gate electrode. The obtained gate insulator was annealed for 1 h at temperatures ranging from 110 to 170 °C in increments of 20 °C for an analysis of the underlying effect of temperature on the properties of P(VDF-co-HFP). The results show that the FET fabricated at the optimized temperature of 150 °C exhibits significantly improved hysteresis loop and on/off ratio. This investigation led to the development of a simple method of designing and preparing an FET with excellent electrical characteristics.
Corresponding author: Jaehoon Park and Eui-Jik KimThis work is licensed under a Creative Commons Attribution 4.0 International License. Cite this article Chintalapalli Jyothi, Jaehoon Park, and Eui-Jik Kim, Optimization of Ferroelectric Phase in Poly(vinylidene fluoride co-hexafluoropropylene) under Different Annealing Conditions, Sens. Mater., Vol. 31, No. 7, 2019, p. 2323-2331. |