To enhance the reliability of sensor interfaces and signal-processing circuits operating in radiation environments, a novel low-power double node upset (DNU)-tolerant latch, termed the low-power double-node upset tolerant (LDUT) latch, is proposed and implemented in this work. The design employs a redundant architecture based on C-elements (CE) and a self-recovery cell (SRC) module, achieving full DNU self-recovery capability through a clock-controlled feedback loop that enhances circuit robustness for sensor-related electronic systems. Simulation results under the Taiwan Semiconductor Manufacturing Company (TSMC) 65 nm CMOS technology demonstrate that the LDUT latch significantly outperforms existing designs in key performance metrics. Dynamic power consumption is reduced to 0.77 μW, representing an improvement of 25.08% compared with the high-performance, low-cost, and DNU-tolerant latch (HLDTL) and 87.3% compared with the DNU-resilient latch (DNURL) design. Further process-voltage–temperature (PVT) analysis shows that the LDUT latch also provides low sensitivity to temperature variations, making it suitable for radiation-hardened sensor applications and high-reliability integrated circuits.