pp. 3065-3072
S&M2322 Research Paper of Special Issue https://doi.org/10.18494/SAM.2020.2725 Published: September 30, 2020 77 GHz Quadrature Frequency Multiplier-by-nine with Superior Suppression for Radar Sensors [PDF] Si-Da Tang, Wei-Hsiang Huang, and Yu-Sheng Lin (Received December 3, 2019; Accepted May 12, 2020) Keywords: CMOS, frequency multiplier, W-band, radar sensor
A 77 GHz quadrature frequency multiplier-by-nine is demonstrated using the 90 nm CMOS process. The implemented multiplier-by-nine is composed of a high conversion gain quadrature frequency tripler with coupled lines as the buffer stage to reduce power consumption and increase power output. This frequency multiplier-by-nine achieves good suppression for the fundamental, second, and other harmonics. The conversion loss is −33 dB at 77 GHz. The DC power consumption is only 5.2 mW. The chip area is 0.46 mm2. This device can help to improve the performance of high-frequency radar sensors.
Corresponding author: Si-Da TangThis work is licensed under a Creative Commons Attribution 4.0 International License. Cite this article Si-Da Tang, Wei-Hsiang Huang, and Yu-Sheng Lin, 77 GHz Quadrature Frequency Multiplier-by-nine with Superior Suppression for Radar Sensors, Sens. Mater., Vol. 32, No. 9, 2020, p. 3065-3072. |